What is illustrated in FIG. 1 is a portion of a shift register unit. As shown in the figure, the shift register unit comprises a pull-up transistor T1, a storage capacitor C, a clock signal input terminal CLK, and a signal output terminal OUT. In an output phase of the shift register unit, the pull-up transistor T1 is turned on, such that a valid signal inputted via the clock signal input terminal CLK is outputted to the signal output terminal OUT. It is required to control the pull-up transistor T1 to be cut off in certain phases of the work cycle of the shift register unit (e.g. a reset phase of the shift register unit) so as to avoid output from the signal output terminal in these phases, thus it is necessary to make the voltage difference between the gate and the source of the pull-up transistor T1 to be zero.
However, as the display device is used, there exists a situation where the pull-up transistor T1 cannot be normally cut off, resulting in abnormal display.